1. When the processor constantly checks the status of an I/O device, this is called:
a. Memory mapped I/O
b. Asynchronous communication
c. Synchronous communication
d. Interrupt-Driven I/O
e. Polling
2. When the processor treats I/O devices as locations in memory and uses the same instructions to access them, this is called:
a. Memory mapped I/O
b. Asynchronous communication
c. Synchronous communication
d. Interrupt-Driven I/O
e. Polling
3. When the processor reads from input or writes to output on every clock cycle, this is called:
a. Memory mapped I/O
b. Asynchronous communication
c. Synchronous communication
d. Interrupt-Driven I/O
e. Polling
4. The difference between a TRAP and an interrupt is:
a. A TRAP results in a special function call, an interrupt does not
b. A TRAP is generated by software, an interrupt is generated by hardware
c. A TRAP is generated by hardware, an interrupt is generated by software
d. A TRAP can disturb registers, an interrupt does not
e. b and d
f. c and d
5. A DMA is used:
a. To transfer data from registers to the ALU
b. To transfer data from the processor to I/O devices
c. To transfer data from memory to I/O devices
d. To transfer data from interrupts to TRAPS
e. To transfer data from the processor to memory
6. A program that interfaces with the hardware or does something other user programs can’t is said to be:
a. High-priority
b. Privileged
c. Low-Priority
d. A subroutine
7. When creating a subroutine in assembly, what needs to be handled?
a. Passing parameters to the subroutine
b. Returning values from the subroutine
c. Returning to the proper location when the subroutine is finished
d. All of the above
e. None of the above
8. The RET instruction:
a. Changes the value in R7
b. Moves control to the address PC + R7
c. Is used to start a subroutine
d. Can be replaced with a JMP R7 instruction
e. Is only used in TRAPs
9. What advantage does Interrupt-Driven I/O have over polling?
a. Interrupt-Driven I/O is synchronous while polling is asynchronous
b. Interrupt-Driven I/O does not require any additional hardware
c. Interrupt-Driven I/O allows the computer to process other tasks while waiting for I/O
d. Interrupt-Driven I/O can be memory-mapped while polling cannot
e. Polling must be implemented with TRAPS and Interrupt-Driven I/O does not
10. The finite state machine that steps through the instruction cycle is located in:
a. The controller
b. The datapath
c. The registers
d. The combinational logic
e. The memory
11. When implementing a datapath, if a register can have its input come from multiple sources, what is necessary?
a. A Multiplexor to select among the inputs
b. A Decoder to select among the inputs
c. A single or-gate to merge the inputs together
d. A single and-gate to merge the inputs together
12. Memory mapping of hardware registers is achieved by:
a. An OS routine (i.e. software) that checks for the mapped address and re-routes the data to the register.
b. The register is directly connected to the memory circuit decoder output of the mapped address.
c. An address Control Logic circuit decodes the requested address and determines whether the main memory or the register is enabled.
d. A separate address bus carries the address to the external registers.
13. The Instruction Set Architecture level of abstraction consists of:
a. A high level language like C to express algorithms
b. A listing of exported functions supported by a machine
c. A specific implementation on silicon
d. Logic gates creating combinational circuits
e. Transistors creating Boolean logic
14. If memory is 16-bit addressable and has 5 address lines to select the item, how many total bytes are stored in memory?
a. 64
b. 32
c. 16
d. 8
e. 5
f. 4
15. In the previous question, how many data lines are necessary?
a. 64
b. 32
c. 16
d. 8
e. 5
f. 4
16. In the von Neumann model, the Program Counter is:
a. A register that stores the next instruction to be executed
b. A register that stores the address of the next instruction to be executed
c. A binary counter that counts how many instructions have been executed
d. A control circuit that steps through a sequence of instructions
e. A register that stores the current location in memory to read and write from
17. If I am currently executing the instruction located at 0x3000 and I execute a PC-Relative jump with offset 0x0024, where is the next instruction I will execute located in memory?
a. 0x3001
b. 0x0024
c. 0x3024
d. 0x3025
e. 0x0025
18. A jump table is:
a. An array of instructions
b. An array of addresses
c. An array of commands
d. An array of jump instructions
e. An array of registers
19. Assembly language instructions (Note: This was thrown out because it was not a complete question)
a. Direct, indirect, and relative
b. Integer, floating point, and character
c. Operations, data movement, and control
d. Input, output, and command
e. Load, store, and arithmetic
20. When an R-S latch as described in class and in the book has the R input held at 0 and the S input held at 1, what is the output?
a. 0
b. 1
c. The previous value
d. Changes rapidly between 0 and 1
21. Which of the following LC-3 instructions can be executed without changing the value of any general purpose register?
a. Add R0, R0, #0
b. And R1, R1, R1
c. Jmp R7
d. BRzp Somewhere
e. All of the above
f. None of the above
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